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continuous rate 10 mbps to 2.7 gbps clock and data recovery ics data sheet adn2817 / adn2818 rev. e document feedback information furnished by analog devices is believ ed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no lic ense is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781 .329.4700 ? 2007C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features serial data input: 10 mbps to 2.7 gbps exceeds itu - t jitter specifications integrated limiting amplifier 5 mv p - p sensitivity (adn2817 only) adjustable slice level: 100 mv (adn2817 only) patented dual - loop clock recovery architecture programmable los detect (adn2817 only) integrated prbs generator and detector no reference clock required loss of lock indicator supports double data rate bit error rate monitor (bermon) or sample phase adjust options rate selectivity without the use of a reference cl ock i 2 c interface to access optional features single - supply operation: 3.3 v low power 650 mw (adn2817) 600 mw (adn2818) 5 mm 5 mm 32 - lead lfcsp applications sonet oc - 1, oc - 3, oc - 12, oc - 48, a nd all associated fec rates fibre channel, 2 fibre channel, g be, hdtv wdm transponders regenerators/repeaters test equipment general description the adn2817/adn2818 provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 mbps to 2.7 gbps. th e adn2817/ adn2818 automatically lock to all data rates without the need for an external reference clock or programming. all sonet jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. all specifications are q uoted for ?40c to +85c ambient temperature, unless otherwise noted. this device, together with a pin diode and a tia preamplifier, can implement a highly integrated, low cost, and low power fiber optic receiver. the adn2817/adn2818 have many optional fea tures available through an i 2 c interface. for example, the user can read back the data rate onto which the adn2817 or adn2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. a be rmon circuit provides an estimate of the received bit error rate (ber) without interruption of the data. alternatively, the user can adjust the data sampling phase to optimize the received ber. the adn2817/adn2818 are available in a compact 5 mm 5 mm, 32- lead, lead frame chip scale package. functional block dia gram loop filter phase det slice adjust (adn2817 only) los detect (adn2817 only) data retiming i 2 c registers loop filter freq/ lock det vcc vee adn2817/adn2818 cf1 cf2 lo l refclkp/refclkn (optional) slicep/ slicen pin nin vref thradj los dataoutp/ dataoutn clkoutp/ clkoutn sck sda vco 06001-001 bermon vber bermode phase shifter ? figure 1 .
adn2817/adn2818 data sheet rev. e | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 jitter specifications ....................................................................... 5 outp ut and timing specifications ............................................. 6 bit error rate monitor specifications ....................................... 8 timing characteristics ................................................................ 9 absolute maximum ratings .......................................................... 10 thermal characteristics ............................................................ 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 12 i 2 c interface timing and internal register description ........... 14 terminology .................................................................................... 18 input sensitivity and input overdrive ..................................... 18 single - ended vs. differential .................................................... 18 los response time ................................................................... 18 jitter specifications ......................................................................... 19 jitter generation ......................................................................... 19 jitter transfer ............................................................................... 19 jitter tolerance ............................................................................ 19 theory of operation ...................................................................... 20 functional description .................................................................. 22 frequency acquisition ............................................................... 22 lock detector operation .......................................................... 22 harmonic detector .................................................................... 23 limiting ampl ifier (adn2817 only) ..................................... 23 slice level adjust (adn2817 only) ........................................ 23 loss of signal (los) detector (adn2817 only) .................. 23 sample phase adjust .................................................................. 24 bit error rate (ber) monitor ................................................... 24 squelch mode ............................................................................. 25 i 2 c interface ................................................................................ 25 reference clock (optional) ...................................................... 26 additional features available via the i 2 c interface ............... 28 applications information .............................................................. 30 pcb design guidelines ............................................................. 30 dc - coupled application .......................................................... 32 coarse data rate readback look - up tabl e ............................... 33 hi_code and lo_code look - up table ................................ 35 outline dimensions ....................................................................... 38 ordering guide .......................................................................... 38
data sheet adn2817/adn2818 rev. e | page 3 of 40 revision history 1/1 3 rev. d to rev. e moved revision histor y section ..................................................... 3 change to table 8 ............................................................................ 15 changes to table 15 ........................................................................ 17 changes to rate selectivity section .............................................. 28 1/1 2 rev. c to rev. d changes to figure 14 ...................................................................... 1 2 updated outline dimensions ........................................................ 37 3/10 rev. b to rev. c changes to features section and applications section ............... 1 changes to thermal resistance section ........................................ 9 added table 6; renumbered sequentially ..................................... 9 changes to table 7 .......................................................................... 10 changes to table 8 .......................................................................... 1 4 changes to table 14 ........................................................................ 1 5 deleted table 16; renumbered sequentially ............................... 16 changes to table 1 6 ........................................................................ 1 6 changes to i 2 c interface section ................................................... 24 changed f ref ratio to div_fref ratio ....................................... 25 changes to initiate frequency acquisition, rate selectivity, double data rate mode, and prbs generator/detector sections ............................................................................................. 27 changes to table 19 ........................................................................ 32 changes to table 20 ........................................................................ 34 2/09 rev. a to rev. b updated outline dimensions ........................................................ 37 change s to ordering guide ........................................................... 37 8 /08 rev. 0 to rev. a changes to features section, general description section, and figure 1 ............................................................................................... 1 added bit rate monitor specifications section and table 4; renumbered sequentially ................................................................ 7 changes to figure 5 and table 6 ................................................... 10 changes to table 7 and table 8 ..................................................... 14 changes to table 14 ........................................................................ 15 added table 15 ................................................................................ 15 added tabl e 16 ................................................................................ 1 6 added sample phase adjust section and bit error rate (ber) monitor section ............................................................................... 23 added figure 32; renumbered sequentially ............................... 24 changes to figure 36 ...................................................................... 29 added exposed pad notation to outli ne dimensions .............. 37 7/07 revision 0: initial version
adn2817/adn2818 data sheet rev. e | page 4 of 40 specifications t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 0.47 f, slicep = slicen = vee, input data pattern: prbs 2 23 ? 1, unless otherwise noted. table 1. parameter conditions min typ max unit quantizer dc characteristics input voltage range at pin or nin, dc - coupled 1.8 2.8 v peak -to - peak differential input pin ? nin 2.0 v input common - mode level dc - coupled (see figure 40, figure 41 , and figure 42) 2.3 2.5 2.8 v differential input sensitivity 2 23 ? 1 prbs, ac - coupled , 1 ber = 1 10 ?10 adn2817 10 5 mv p -p adn2818 200 mv p -p quantizer ac characteristics data rate 10 2700 mbps s11 at 2.5 ghz ? 15 db input resistance differential 100 ? input capacitance 0.65 pf quantizer slice adjustment adn2817 only gain slicep ? slicen = 0.5 v 0.10 0.11 0.13 v/v differential control voltage input slicep ? slicen ? 0.95 + 0.95 v control voltage range dc level @ slicep or slicen vee 0.95 v slice threshold offset 1 mv loss of signal detect (los) adn2817 only loss of signal detect range (see figure 6) r thresh = 0 ? 14.2 20.0 mv r thresh = 100 k ? 2.1 5.0 mv hysteresis (electrical) oc -48 r thresh = 0 ? 6.2 8.2 db r thresh = 100 k ? 4.7 7.7 db oc -1 r thresh = 0 ? 4.9 7.5 db r thresh = 10 k ? 3.0 7.3 db los assert time dc - coupled 2 450 ns los deassert time dc - coupled 2 500 ns loss of lock detect (lol) vco frequency error for lol assert with respect to nominal 1000 ppm vco frequency error for lol deassert with respect to nominal 250 ppm lol response time oc -48 1.0 s oc -12 1.0 s 10 mbps 500 s acquisition time lock to data mode oc -48 1.3 ms oc -12 2.0 ms oc -3 3.4 ms oc -1 9.8 ms 10 mbps 40.0 ms optional lock to refclk mode 10.0 ms data rate readback accuracy coarse readb ack see table 19 10 % fine readback in addition to refclk accuracy 100 ppm
data sheet adn2817/adn2818 rev. e | page 5 of 40 parameter conditions min typ max unit power supply voltage 3.0 3.3 3.6 v current adn2817 210 247 ma adn2818 180 217 ma operating temperature range ?40 +85 c 1 pin and nin should be differentially driven and ac - coupled for optimum sensitivity. 2 when ac - coupled, the los assert and deassert time is dominated by the rc time c onstant of the ac coupling capacitor and the 50 ? input termination of the adn2817 input stage. jitter specifications t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 0.47 f, slicep = slicen = vee, input data pattern: prbs 2 23 ? 1, unless otherwise noted. table 2. parameter conditions min typ max unit phase - locked loop cha racteristics jitter transfer bandwidth oc -48 548 839 khz oc -12 93 137 khz oc -3 30 40 khz jitter peaking oc -48 0 0.03 db oc -12 0 0.03 db oc - 3 0 0.03 db jitter generation oc -48 12 khz to 20 mhz 0.001 0.003 ui rms 0.02 0.046 ui p -p oc -12 12 khz to 5 mhz 0.001 0.004 ui rms 0.01 0.036 ui p -p oc -3 12 khz to 1.3 mhz 0.001 0.004 ui rms 0.01 0.023 ui p -p jitter tolerance 2 23 ? 1 prbs oc -48 600 hz 1 92.0 ui p -p 6 khz 1 20.0 ui p -p 100 khz 7.0 ui p -p 1 mhz 1 1.00 ui p -p 20 mhz 0.53 ui p -p oc -12 30 hz 1 100.0 ui p -p 300 hz 1 44.0 ui p -p 25 khz 7.35 ui p -p 250 khz 1 1.00 ui p - p 5 mhz 0.52 ui p -p oc -3 30 hz 1 50.0 ui p -p 300 hz 1 23.5 ui p -p 6500 hz 6.71 ui p -p 65 khz 1 1.00 ui p -p 130 khz 0.54 ui p -p 1 jitter tolerance of the adn2817/adn2818 at these jitter frequencies is better than what the test equipment is able to measure .
adn2817/adn2818 data sheet rev. e | page 6 of 40 output and timing sp ecifications table 3. parameter conditions min typ max unit cml ouput charac teristics (clkoutp/clkoutn, dataoutp/dataoutn) single - ended output swing , v se s ee figure 3 300 350 600 mv differential output swing , v diff see figure 3 600 700 1200 mv output voltage high , v oh vcc v low , v ol vcc ? 0.6 vcc ? 0.35 vcc ? 0.3 v cml outputs timing rise time 20% to 80% 80 112 ps fall time 80% to 20% 80 123 ps setup time , t s see figure 2 , oc -48 150 200 250 ps hold time, t h s ee figure 2 , oc -48 150 200 250 ps setup time , t ddrs s ee figure 4 , oc -48 140 170 200 ps hold time, t ddrh s ee figure 4 , oc -48 200 230 260 ps i 2 c interface dc characteristics lvcmos input voltage high , v ih 0.7 vcc v low , v il 0.3 vcc v input current v in = 0.1 vcc or v in = 0.9 vcc ? 10.0 +10.0 a output low voltage v ol , i ol = 3.0 ma 0.4 v i 2 c interface timing see figure 22 sck clock frequency 400 khz sck pulse width high high , t high 600 ns low , t low 1300 ns start condition hold time , t hd;sta 600 ns setup time , t su;sta 600 ns data setup time , t su;dat 100 ns hold time , t hd;dat 300 ns sck/sda rise/fall time , t r /t f 20 + 0.1 cb 300 ns stop condition setup time , t su;sto 600 ns bus free time between a stop and a start , t buf 1300 ns refclk characteristics optional lock to refclk mode input voltage range at refclkp or refclkn v il 0 v v ih vcc v minimum differential input drive 100 mv p -p reference frequency 10 200 mhz require d accuracy 100 ppm
data sheet adn2817/adn2818 rev. e | page 7 of 40 parameter conditions min typ max unit lvttl dc input characteristics input voltage high, v ih 2.0 v low, v il 0.8 v input current high i ih , v in = 2.4 v +5 a low i il , v in = 0.4 v ? 5 a lvttl dc output characteristics output voltage high v oh , i oh = ? 2.0 ma 2.4 v low v ol , i ol = +2.0 ma 0.4 v
adn2817/adn2818 data sheet rev. e | page 8 of 40 bit error rate monit or specifications t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 0.47 f, slicep = slicen = vee, input data pattern: prbs 2 23 ? 1, unless otherwise noted. table 4. parameter conditions min typ max unit bermon extrapolation mode i 2 c- controlled eye profiling final computed ber accuracy input ber range 1 10 ?3 to 1 10 ?12 , input deterministic jitter ( dj ) < 0.4 ui, dj ceiling > 1 10 ?2 ; asymmetry < 0.1 ui; requires external data processing algorithms to implement q factor extrapolation 1 decades number of bits (n umbits ) number of data bits to collect pseudo errors; user programmable in increment factors of 2 3 over the ran ge 2 18 to 2 39 2 18 2 39 ui pseudo ber ( pber ) measurement time numbits / data rate sec ber range 5 10 ?2 ber sample phase adjust resolution 6 degrees sample phase adjust accuracy < 6 degrees sample phase adjust range with respect to normal sa mpling instant ?0.5 +0.5 ui minimum input signal level differential peak to peak 4 mv power increase ber en abled 160 mw ber standby 77 mw bermon voltage output mode analog voltage output ber accuracy input ber r ange 1 10 ?3 to 1 10 ?9 , i nput dj = 0 ui, dj ceiling > 1 10 ?2 ; asymmetry = 0 ui; ber is read as a voltage on the vber pin, when the ber mode pin = vee 1 decades input ber range 1 10 ?3 to 1 10 ?9 , input dj = 0.2 ui, dj ceiling > 1 10 ?2 ; asymmetry = 0 ui; ber is read a s a voltage on the vber pin, when the ber mode pin = vee +1/?2 decades numbits number of data bits to collect pseudo errors 2 27 ui measurement time 2.5 gb ps 0.054 sec 1 gb ps 0.134 sec 155 mb ps 0.865 sec 10 mb ps 1.34 s ec vber voltage ra nge via 3 k? resistor to vee 0.1 0.9 v minimum input signal level differential peak to peak 4 mv power increase ber voltage mode 160 mw sample phase adjust mode sample phase adjust step size monotonic 6 degrees sample phase adjust accurac y < 6 degrees sample phase adjust range with respect to normal sampling instant ?0.5 +0.5 ui power increase 160 mw
data sheet adn2817/adn2818 rev. e | page 9 of 40 timing characteristics clkoutp dataoutp/ dataoutn t s t h 06001-002 figure 2. default mode output timing outp outn outp ? outn 0v v se v cml v se v diff 06001-003 figure 3. single-ended vs. differential output specifications clkoutp/ clkoutn t ddrs t ddrh dataoutp/ clkoutn 06001-042 figure 4. double data rate mode output timing
adn2817/adn2818 data sheet rev. e | page 10 of 40 absolute maximum rat ings t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 0.47 f, slicep = slicen = vee, unless otherwise not ed. table 5. parameter rating supply voltage (vcc) 4.2 v input voltage (all inputs) minimum vee ? 0.4 v maximum vcc + 0.4 v junction temperature, maximum 125c storage temperature range ? 65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional oper ation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characte ristics thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages, on a 4 - layer board with the exposed paddle soldered to vee . table 6 . thermal resistance package type ja unit 32- lead lfcsp 28 c/w esd caution
data sheet adn2817/adn2818 rev. e | page 11 of 40 pin configuration an d function descripti ons vber vcc vee dataoutp dataoutn squelch clkoutp clkoutn thradj refclkp refclkn vcc vee cf2 cf1 lol bermode vcc vref nin pin slicep slicen vee vcc vee los sda sck saddr5 vcc vee 06001-004 notes 1. exposed p addle on the bot t om of the p ackage must be connected t o vee. pin 1 indic a t or 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 1 1 12 13 14 15 16 32 31 30 29 28 27 26 25 t o p view (not to scale) adn2817/ adn2818 figure 5 . pin configuration table 7 . pin function descriptions pin no. mnemonic type 1 description 1 bermode d i set this pin to logic low to enable analog voltage output mode for ber monitor. 2 vcc p power for input stage, los. 3 vref ao internal vref voltage. decouple to ground with a 0.1 f capacitor. 4 nin ai differential data input. cml. 5 pin ai dif ferential data input. cml. 6 slicep ai differential slice level adjust input. 7 slicen ai differential slice level adjust input. 8 vee p gnd for the limiting amplifier, los. 9 thradj ai los threshold setting resistor. 10 refclkp di differential ref clk input. 10 mhz to 200 mhz. 11 refclkn di differential refclk input. 10 mhz to 200 mhz. 12 vcc p vco power. 13 vee p vco ground . 14 cf2 ao frequency loop capacitor. 15 cf1 ao frequency loop capacitor. 16 lol do loss of lock indicator. active high , lvttl. 17 vee p fll detector ground . 18 vcc p fll detector power. 19 saddr5 di slave address bit 5. 20 sck di i 2 c clock input. 21 sda di i 2 c data input. 22 los do loss of signal detect output. active high, lvttl. 23 vee p output buffer, i 2 c ground . 24 vcc p output buffer, i 2 c power. 25 clkoutn do differential recovered clock output. cml. 26 clkoutp do differential recovered clock output. cml. 27 squelch di disable clock and data outputs. active high, lvt t l. 28 dataoutn do differential recove red data output. cml. 29 dataoutp do differential recovered data output. cml. 30 vee p phase detector, phase shifter ground . 31 vcc p phase detector, phase shifter power. 32 vber ao this pin represents ber when analog bermon is enabled with 3 k? to vee . ep epad p exposed paddle. the exposed paddle on the bottom of the package must be connected to vee. 1 p = power, ai = analog input, ao = analog output, di = digital input, do = digital output.
adn2817/adn2818 data sheet rev. e | page 12 of 40 typical performance characteristics 1 10 100 r th ( ?) 1k 100k 10k 1m 0 tri p point (mv p-p) 06001-005 0.00 2 0.00 4 0.00 6 0.00 8 0.0 10 0.0 12 0.0 14 0.0 16 0.0 18 0.0 20 figure 6 . los comparator trip point programming ?20 ?15 ?10 ?5 0 5 100 1k 10k 100k 1m 06001-032 jitter frequency (hz) gain (db) sonet adn2817 figure 7 . jitter transfer, oc - 1 ?20 ?15 ?10 ?5 0 5 100 1k 10k 100k 1m 10m 06001-034 jitter frequency (hz) gain (db) sonet adn2817 figure 8 . jitter transfer, oc - 3 06001-040 50ps/div 200mv/div figure 9 . output eye, oc - 48 0.1 10 100 1k 10k 100k 1m 06001-039 jitter frequency (hz) jitter amplitude (ui) 1 10 100 adn2817 equipment limit sonet gr-253 core 004 figure 10 . jitter tolerance, oc - 1 0.1 10 100 1k 10k 100k 10m 1m 06001-038 jitter frequency (hz) jitter amplitude (ui) 1 10 100 adn2817 equipment limit sonet gr-253 core 004 figure 11 . jitter tolerance, oc - 3
data sheet adn2817/adn2818 rev. e | page 13 of 40 ?20 ?15 ?10 ?5 0 5 1k 10k 100k 1m 10m 06001-033 jitter frequency (hz) gain (db) sonet adn2817 figure 12 . jitter transfer, oc - 12 ?20 ?15 ?10 ?5 0 5 10k 100k 1m 10m 100m 06001-035 jitter frequency (hz) gain (db) sonet adn2817 figure 13 . jitter transfer, oc - 48 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 clkoutp adn2817 clkoutn adn2817 06001-043 data rate (hz) output swing (v) 100m 600m 1.1g 1.6g 2.1g 2.6g 3.1g figure 14 . output swing vs. data rate 0.1 10 100 1k 10k 100k 10m 1m 06001-037 jitter frequency (hz) jitter amplitude (ui) 1 10 100 1000 adn2817 equipment limit sonet gr-253 core 004 figure 15 . jitter tolerance, oc - 12 0.1 10 100 1k 10k 100k 100m 10m 1m 06001-036 jitter frequency (hz) jitter amplitude (ui) 1 10 100 1000 adn2817 equipment limit sonet gr-253 core 004 figure 16 . jitter tolerance, oc - 48 06001-041 input level (mv) bit error rate 0.000000001 0.00000001 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 figure 17 . bit error rate vs. input level
adn2817/adn2818 data sheet rev. e | page 14 of 40 i 2 c-interface timing and intern al register description 1a500000x msb = 1 set by pin 19 0 = wr 1 = rd slave address [6:0] r/w ctrl. 06001-007 figure 18. slave address configuration s slave addr, lsb = 0 (wr) a(s) a(s) a(s) data sub addr a(s) p data 06001-008 figure 19. i 2 c write data transfer s s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a(m) = lack of acknowledge by master s slave addr, lsb = 0 (wr) slave addr, lsb = 1 (rd) a(s) a(s) sub addr a(s) data a(m) data p a(m) 0 6001-009 figure 20. i 2 c read data transfer start bit s stop bit p ack ack wr ack d0 d7 a0 a7 a5 a6 sladdr[4:0] slave address sub address data sub addr[6:1] data[6:1] sck sda 06001-010 figure 21. i 2 c data transfer timing t buf sda ssps sck t f t low t r t f t hd;sta t hd;dat t su;dat t high t su;sta t su;sto t hd;sta t r 06001-011 figure 22. i 2 c port timing diagram
data sheet adn2817/adn2818 rev. e | page 15 of 40 table 8 . internal register map 1 reg name r/w addr d7 d6 d5 d4 d3 d2 d1 d0 freq0 r 0x00 msb lsb freq1 r 0x01 msb lsb freq2 r 0x02 0 msb lsb rate r 0x03 coarse_rd[8:1] misc r 0x04 x x los s tatus static lol lol s tatus data rate measurement complete x coarse_rd[0] (lsb) ctrla w 0x08 f ref r ange data r ate/div_fref r atio measure data rate lock to refclk ctrla_rd r 0x05 readback ctrla ctrlb w 0x09 config lol reset misc[4] initiate freq acquisitio n 0 reset misc[2] 0 0 0 ctrlb_rd r 0x06 readback ctrlb ctrlc w 0x11 0 0 0 0 0 config los squelch m ode 0 ctrld w 0x22 cdr b ypass disable dataout b uffer disable clkout b uffer 0 initiate prbs s equence prbs m ode ctrle/berctlb 2 w 0x1f 0 0 enable bermon ber stdby mode 0 prbs/ddr enable and output mode sel_mode w 0x34 0 0 0 0 limited rate mode 0 clk holdover mode 0 hi_code w 0x35 hi_code[8:1] lo_code w 0x36 lo_code[8:1 ] code_lsb w 0x39 0 0 0 0 0 0 hi_code[0] (lsb) lo_code[0] (lsb) berctla w 0x1e ber t imer (numbits) 0 ber start pulse error count byte select , for example, 011 = byte 3 of 5 (numerrors[39:0]) bersts r 0x20 x x x x x x x end of ber m easur e ment (eobm) ber _res r 0x21 ber_res[7:0], one byte of pseudo ber measurement result (numerrors[39:0]) ber_dac r 0x24 x x ber_dac[5:0], input to ber dac in analog bermon mode phase w 0x37 0 0 phase [5:0], twos compl e ment sample phase adjustment, phase code range is from ?30 decimal to +30 decimal, which gives a sampling phase offset range from ?0.5 ui to +0.5 ui; for example, phase = 111010 is?6 decimal, which gives a sampling phase offset of ?6/+60 = ?0.1 ui 1 x = dont care. 2 both ctrle and berc t lb registers are used, depending on the application. table 9 . miscellaneous register, m isc los status static lol lol status data rate measurement complete coarse_rd[0] (lsb) d7 d6 d5 d4 d3 d2 d1 d0 x x 0 = no loss of signal 0 = waiting for next lol 0 = locked 0 = measuring data rate x coarse_rd[0] 1 = loss of signal 1 = static lol un til reset 1 = acquiring 1 = measurement complete
adn2817/adn2818 data sheet rev. e | page 16 of 40 table 10 . control register, ctrla f ref range data rate/div_fref ratio measure data rate lock to refclk d7 d6 range d5 d4 d3 d2 ratio d1 d0 set to 0 set to 0 10 mhz to 25 mhz 0 0 0 0 1 set to 1 to measure data rate 0 = lock to input data set to 0 set to 1 25 mhz to 50 mhz 0 0 0 1 2 1 = lock to reference clock set to 1 set to 0 50 mhz to 100 mhz 0 0 1 0 4 set to 1 set to 1 100 mhz to 200 mhz n 2 n 1 0 0 0 256 table 11 . control register, ctrlb config lol reset misc[4] initiate freq acq uisition reset misc[2] d7 d6 d5 d4 d3 d2 d1 d0 0 = lol pin normal operation 1 = lol pin is static lol write a 1 followed by 0 to reset misc[4] write a 1 fol lowed by 0 to initiate a frequency acquisition set to 0 write a 1 followed by 0 to reset misc[2] set to 0 set to 0 set to 0 table 12 . control register, ctrlc configure los squelch mode d7 d6 d5 d4 d3 d2 d1 d0 set to 0 set to 0 set to 0 set to 0 set to 0 0 = active high los 0 = squelch clk and data set to 0 1 = active low los 1 = squelch clk or data table 13 . control register, ctrld cdr bypass disable dataout buffer disable clkout buffe r initiate prbs sequence prbs mode d7 d6 d5 d4 d3 d2 d1 d0 function 0 = cdr enabled 0 = data buffer enabled 0 = clk buffer enabled set to 0 write a 1 followed by 0 to initiate a prbs generate sequence 0 0 0 power - down prbs 1 = cdr disabled 1 = data b uffer disabled 1 = clk buffer disabled 0 0 1 generate mode 1 0 0 detect mode table 14 . control register s , ctrle /berct lb enable bermon ber stdby mode prbs/ddr enable and output mode d7 d6 d5 d4 d3 d2 d1 d0 function set to 0 set to 0 1 = bermon enabled 0 = bermon disabled 1 = p lace bermon in low power standby mode 0 = bermon ready set to 0 0 0 0 normal data rate output mode 0 0 1 offset d ecision c ircuit (odc) output mode 1 0 1 0 enable ddr mode (double data ra te mode) 0 1 1 offset d ecision c ircuit (odc) output in ddr mode 1 1 0 1 enable prbs detector/generator all other combinations reserved 1 see an - 941 application note, ber monitor user guide .
data sheet adn2817/adn2818 rev. e | page 17 of 40 table 15. mode select register, sel_mode clk holdover mode d7 d6 d5 d4 d3 d2 d1 d0 set to 0 set to 0 set to 0 set to 0 default 0 limited rate enable = 1 set to 0 set to 1 for clock holdover mode set to 0 table 16. ber control register, berctla ber timer (numbits ) ber start pulse error count byte select (numerrors[39:0]) d7 d6 d5 no . of bits d4 d3 d2 d1 d0 byte selection 0 0 0 2 18 bits set to 0 write a 1 followed by a 0 to initiate ber measurement 0 0 0 byte 0 0 0 1 2 21 bits 0 0 1 byte 1 0 1 0 2 24 bits 0 1 0 byte 2 0 1 1 2 27 bits 0 1 1 byte 3 1 0 0 2 30 bits 1 0 0 byte 4 1 0 1 2 33 bits 1 1 0 2 36 bits 1 1 1 2 39 bits
adn2817/adn2818 data sheet rev. e | page 18 of 40 terminology input sensitivity an d input overdrive sensitivity and overdrive specifications for the quantizer involve offset voltage, gain, and noise. the relationship between the logic output of the quantizer and the analog voltage input is shown in figure 23. for sufficiently large positive input voltages, the output is always logic 1 and, similarly for negative inputs, the output is always logic 0. however, the transitions between output logic level 1 and output logic level 0 are not at precisely defined input voltage levels but occur over a range of input voltages. within this range of input voltages, the output may be either 1 or 0, or it may even fail to attain a valid logic state. the width of this zone is determined by the input voltage noise of the quantizer. the center of the zone is the quantizer input offset voltage. input overdrive is the magnitude of signal required to guarantee the correct logic level with 1 10 ?10 confidence level. noise output input (v p-p) offset overdrive sensitivity (2 overdrive) 1 0 06001-012 figure 23. input sensitivity and input overdrive single-ended vs. differential ac coupling is typically used to drive the inputs to the quantizer. the inputs are internally dc biased to a common-mode potential of ~2.5 v. driving the adn2817/adn2818 single-ended and observing the quantizer input with an oscilloscope probe at the point indicated in figure 24 shows a binary signal with an average value equal to the common-mode potential and instantaneous values both above and below the average value. it is convenient to measure the peak-to-peak amplitude of this signal and call the minimum required value the quantizer sensitivity. referring to figure 24, because both positive and negative offsets need to be accommodated, the sensitivity is twice the overdrive. the adn2817 quantizer typically has 5 mv p-p sensitivity. the adn2818 does not have a limiting amplifier at its input. the input sensitivity for the adn2818 is 200 mv p-p. + ? quantizer 50? 50? 3k? 2.5v vref scope probe pin vref 10mv p- p 06001-013 figure 24. single-ended sensitivity measurement differentially driving the adn2817 (see figure 25), sensitivity seems to improve from observing the quantizer input with an oscilloscope probe. this is an illusion caused by the use of a single- ended probe. a 5 mv p-p signal appears to drive the adn2817 quantizer. however, the single-ended probe measures only half the signal. the true quantizer input signal is twice this value because the other quantizer input is a complementary signal to the signal being observed. scope probe pin 50 ? 3k ? 2.5v 50 ? vref quantizer + ? nin 5mv p- p vref 5mv p-p vref 06001-014 figure 25. differential sensitivity measurement los response time the los response time is the delay between the removal of the input signal and the indication of the loss of signal at the los output, pin 22. when the inputs are dc-coupled, the los assert time of the adn2817 is 450 ns typically and the deassert time is 500 ns typically. in practice, the time constant produced by the ac coupling at the quantizer input and the 50 on-chip input termination determine the los response time.
data sheet adn2817/adn2818 rev. e | page 19 of 40 jitter specifications the adn2817/adn2818 cdr is desi gned to achieve the best bit error rate (ber) performance and exceeds the jitter transfer, generation, and tolerance specifications proposed for sonet/sdh equipment defined in the telcordia? technologies specification. jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in unit intervals (ui), where 1 ui = 1 bit period. jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. jitter on the recovered clock causes jitter on the retimed data. the following sections briefly summarize the specifications of jitter generation, transfer, and tolerance in accordance with the telcordia document ( gr-253-core , issue 3, september 2000) for the optical interface at the equipment level and the adn2817/adn2818 performance with respect to those specifications. jitter generation the jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input. for oc-48 devices, the band-pass filter has a 12 khz high-pass cutoff frequency with a roll-off of 20 db/decade and a low-pass cutoff frequency of at least 20 mhz. the jitter generated must be less than 0.01 ui rms and must be less than 0.1 ui p-p. jitter transfer the jitter transfer function is the ratio of the jitter on the output signal to the jitter applied on the input signal vs. the frequency. this parameter measures the limited amount of the jitter on an input signal that can be transferred to the output signal (see figure 26). 0.1 acceptable range f c jitter frequency (khz) slope = ?20db/decade jitter gain (db) 0 6001-015 figure 26. jitter transfer curve jitter tolerance the jitter tolerance is defined as the peak-to-peak amplitude of the sinusoidal jitter applied on the input signal, which causes a 1 db power penalty. this is a stress test intended to ensure that no additional penalty is incurred under the operating conditions (see figure 27). 15.00 1.50 0.15 f 0 f 1 f 2 f 3 f 4 jitter frequency (khz) slope = ?20db/decade input jitte r amplitude (ui p-p) 06001-016 figure 27. sonet jitter tolerance mask
adn2817/adn2818 data sheet rev. e | page 20 of 40 theory of operation the adn2817/adn2818 are delay- and phase-locked loop circuits for clock recovery and data retiming from an nrz encoded data stream. the phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. a high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter. a separate phase control loop, composed of the vco, tracks the low frequency components of input jitter. the initial frequency of the vco is set by a third loop, which compares the vco frequency with the input data frequency and sets the coarse tuning voltage. the jitter tracking phase- locked loop controls the vco by the fine-tuning control. the delay- and phase-locked loops together track the phase of the input data signal. for example, when the clock lags input data, the phase detector drives the vco to a higher frequency and increases the delay through the phase shifter; both of these actions serve to reduce the phase error between the clock and data. the faster clock picks up phase, while, simultaneously, the delayed data loses phase. because the loop filter is an integrator, the static phase error is driven to zero. another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second-order phase-locked loop, and this zero is placed in the feedback path and, thus, does not appear in the closed-loop transfer function. jitter peaking in a conventional second-order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function. because this circuit has no zero in the closed-loop transfer, jitter peaking is minimized. the delay- and phase-locked loops together simultaneously provide wideband jitter accommodation and narrow-band jitter filtering. the linearized block diagram in figure 28 shows that the jitter transfer function, z(s)/x(s), is second-order low-pass, providing excellent filtering. note that the jitter transfer has no zero, unlike an ordinary second-order phase-locked loop. this means that the main pll loop has virtually zero jitter peaking (see figure 29). this makes this circuit ideal for signal regene- rator applications, where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation. the error transfer, e(s)/x(s), has the same high-pass form as an ordinary phase-locked loop. this transfer function is free to be optimized to give excellent wideband jitter accommodation, because the jitter transfer function, z(s)/x(s), provides the narrow-band jitter filtering. x(s) z(s) recovered clock e(s) input data d/sc psh o/s 1/n d = phase detector gain o = vco gain c = loop integrator p sh = phase shifter gain n = divide ratio = 1 cn do s 2 + n psh o s + 1 z ( s ) x ( s ) jitter transfer function = s 2 s 2 d psh c s ++ do cn e ( s ) x ( s ) tracking error transfer function 06001-017 figure 28. adn2817/adn2818 pll/dll architecture adn28xx z(s) x(s) frequency (khz) jitter peakin g in ordinary pll jitter gain (db) o n psh d psh c 06001-018 figure 29. adn2817/adn2818 jitter response vs. conventional pll the delay- and phase-locked loops contribute to overall jitter accommodation. at low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. in this case, the vco is frequency modulated and jitter is tracked as in an ordinary phase-locked loop. the amount of low frequency jitter that can be tracked is a function of the vco tuning range. a wider tuning range gives larger accommodation of low frequency jitter. the internal loop control voltage remains small for small phase errors, so the phase shifter remains close to the center of its range and thus contributes little to the low frequency jitter accommodation.
data sheet adn2817/adn2818 rev. e | page 21 of 40 at medium jitter frequencies, the gain and tuning range of the vco are not large enough to track input jitter. in this case, the vco control voltage becomes large and saturates, and the vco frequency dwells at one extreme of its tuning range or the other. the size of the vco tuning range, therefore, has only a small effect on the jitter accommodation. the delay - locked loop control voltage is now larger, and so the p hase shifter takes on the burden of tracking the input jitter. the phase shifter range, in ui, can be seen as a broad plateau on the jitter tolerance curve. the phase shifter has a minimum range of 2 ui at all data rates. the gain of the loop integrator i s small for high jitter frequencies, so that larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. large phase errors at high jitter frequencies cannot be tolerated. in this region, the gain of the integrator determines the jitter accommodation. because the gain of the loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. at the highest frequencies, the loop gain is very small, and littl e tuning of the phase shifter can be expected. in this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. the jitter accommodation is roughly 0.5 ui in this region . the corner frequency between the declining slope and the flat region is the closed - loop bandwidth of the delay - locked loop, which is roughly 3 mhz at oc - 48.
adn2817/adn2818 data sheet rev. e | page 22 of 40 functional descripti on frequency acquisitio n the adn2817/adn2818 acquire frequency from the data over a range of data frequencies from 10 mbps to 2.7 gbps. the lock detector circuit compares the frequency of the vco and the frequency of the incoming data. when these frequencies differ by more than 1000 ppm, lol is asserted. this initiates a fre - q uency acquisition cycle. the vco frequency is reset to the bottom of its range, which is 10 mhz. the frequency detector compares this vco frequency and the incoming data frequency and increments the vco frequency, if necessary. initially, the vco frequency is incremented in large steps to aid fast acquisi - tion. as the vco frequency approaches the data frequency, the step size is reduced until the vco frequency is within 250 ppm of the data frequency, at which point lol is deasserted. once lol is deasserted, the frequency - locked loop is turned off. the phase - and delay - locked loop (pll/dll) pulls in the vco frequency until the vco frequency equals the data frequency. the frequency loop requires a single external capacitor between cf1 and cf2, pin 14 and pin 1 5. a 0.47 f 20%, x7r ceramic chip capacitor with <10 na leakage current is recommended. leakage current of the capacitor can be calculated by dividing the maximum voltage across the 0.47 f capacitor, ~3 v, by the insulation resistance of the capacitor. the insulation resistance of the 0.47 f capacitor should be greater than 300 m?. lock detector operat ion the lock detector on the adn2817/adn2818 has three modes of operation: normal mode, refclk mode, and static lol mode. normal mode in normal mode, the adn2817/adn2818 function as continuo us rate cdrs that lock onto any data rate from 10 mbps to 2.7 gbps without the use of a reference clock as an acquisition aid. in this mode, the lock detector monitors the frequency difference between the vco and the input data frequency, and deasserts the loss of lock signal that appears on lol (pin 16) when the vco is within 250 ppm of the data frequency. this enables the delay - and phase - locked loop (dll/pll), which pulls the vco frequency in the remaining amount and acquires phase lock. when locked, if the input frequency error exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted and control returns to the frequency loop, which begins a new frequency acquisition starting at the lowest point in the vco operating range, 10 mhz. the lol pin remain s asserted until the vco locks onto a valid input data stream to within 250 ppm frequency error. this hysteresis is shown in figure 30. lo l 0 ?250 250 1000 f vco error (ppm) ?1000 1 06001-019 figure 30 . transfer function of lol lol detector operation using a r eference clock in this mode, a reference clock is used as an acquisition aid to lock the adn2817/adn2818 vco. lock to reference mode is enabled by setting ctrla[0] to 1. the user also needs to write to the ctrla[7:6] and ctrla[5:2] bits to set the referen ce frequency range and the divide ratio of the data rate with respect to the reference frequency. for more details, see the reference clock (optional) section. in this mode, the lock detector monitors the difference in frequency b etween the divided down vco and the divided down reference clock. the loss of lock signal, which appears on lol (pin 16), is deasserted when the vco is within 250 ppm of the desired frequency. this enables the dll/ pll, which pulls the vco frequency in the remaining amount with respect to the input data and acquires phase lock. once locked, if the input frequency error exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted and control returns to the frequency loop, which reacquires with respect to t he reference clock. the lol pin remains asserted until the vco frequency is within 250 ppm of the desired frequency. this hysteresis is shown in figure 30. static lol mode the adn2817/adn2818 implement a static lol feature, which i ndicates if a loss o f lock conditio n has ever o ccurred and remains asserted, even if the adn2817/adn2818 regain lock, until the static lol bit is manually reset. i 2 c r egister b it misc[4] is the static lol bit. if there is ever an occurrence of a loss of lo ck condition, this bit is internally asserted to l ogic high. the misc[4] bit remains high even after the adn2817/adn2818 reacquire lock to a new data rate. this bit can be reset by writing a 1 followed by 0 to i 2 c register bit ctrlb[6]. when reset, the mis c[4] bit remains deasserted until another loss of lock condition occurs. writing a 1 to i 2 c register bit ctrlb[7] causes the lol pin, pin 16, to become a static lol indicator. in this mode, the lol pin mirrors the contents of the misc[4] bit and has the fu nction - ality described previously . the ctrlb[7] bit defaults to 0. in this mode, the lol pin operates in the normal operating mode, that is, it is asserted only when the adn2817/ adn2818 are in acquisition mode and deasserts when the adn2817/adn2818 reacqu ire lock.
data sheet adn2817/adn2818 rev. e | page 23 of 40 harmonic detector the adn2817/adn2818 provide a harmonic detector, which detects whether the input data has changed to a lower harmonic of the data rate onto which the vco is currently locked. for example, if the input data instantaneously changes from an oc-48, 2.488 gbps to an oc-12, 622.080 mbps bit stream, this could be perceived as a valid oc-48 bit stream, because the oc-12 data pattern is exactly 4 slower than the oc-48 pattern. therefore, if the change in data rate is instantaneous, a 101 pattern at oc-12 is perceived by the adn2817/adn2818 as a 111100001111 pattern at oc-48. if the change to a lower harmonic is instantaneous, a typical cdr could remain locked at the higher data rate. the adn2817/adn2818 implement a harmonic detector that automatically identifies whether the input data has switched to a lower harmonic of the data rate onto which the vco is currently locked. when a harmonic is identified, the lol pin is asserted and a new frequency acquisition is initiated. the adn2817/ adn2818 automatically lock onto the new data rate, and the lol pin is deasserted. however, the harmonic detector does not detect higher har- monics of the data rate. if the input data rate switches to a higher harmonic of the data rate onto which the vco is currently locked, the vco loses lock, the lol pin is asserted, and a new frequency acquisition is initiated. the adn2817/adn2818 automatically lock onto the new data rate. the time to detect lock to harmonic is 16,384 (t d / ) where: 1/ t d is the new data rate. for example, if the data rate is switched from oc-48 to oc-12, then t d = 1/622 mhz. is the data transition density. most coding schemes seek to ensure that = 0.5, for example, prbs or 8b/10b encoding. when the adn2817/adn2818 is placed in lock to reference mode, the harmonic detector is disabled. limiting amplifier (adn2817 only) the limiting amplifier on the adn2817 has differential inputs (pin/nin) that internally terminate with 50 to an on-chip voltage reference (vref = 2.5 v typically). the inputs are typically ac-coupled externally, although dc coupling is possible as long as the input common-mode voltage remains above 2.5 v (see figure 40, figure 41, and figure 42). input offset is factory trimmed to achieve better than 6 mv typical sensitivity with minimal drift. the limiting amplifier can be driven differentially or single-ended. slice level adjust (adn2817 only) the quantizer slicing level can be offset by 100 mv to mitigate the effect of amplified spontaneous emission (ase) noise or duty cycle distortion by applying a differential voltage input of up to 0.95 v to slicep/slicen inputs. if no adjustment of the slice level is needed, slicep/slicen should be tied to vee. the gain of the slice adjustment is ~0.1 v/v. loss of signal (los) detector (adn2817 only) the receiver front-end los detector circuit detects when the input signal level has fallen below a user-adjustable threshold. the threshold is set with a single external resistor from pin 9, thradj, to vee. the los comparator trip point vs. resistor value is shown in figure 6. if the input level to the adn2817 drops below the programmed los threshold, the output of the los detector, pin 22 (los), is asserted to a logic 1. the los detector response time is 450 ns by design but is dominated by the rc time constant in ac- coupled applications. the los pin defaults to active high. however, by setting bit ctrlc[2] to 1, the los pin is configured as active low. there is typically 6 db of electrical hysteresis designed into the los detector to prevent chatter on the los pin. this means that, if the input level drops below the programmed los threshold causing the los pin to assert, the los pin is not deasserted until the input level has increased to 6 db (2) above the los threshold (see figure 31). 06001-020 hysteresis los output input level los threshold t input voltage (v diff ) figure 31. adn2817 los detector hysteresis the los detector and the slice level adjust can be used simul- taneously on the adn2817. this means that any offset added to the input signal by the slice adjust pins does not affect the los detector measurement of the absolute input level.
adn2817/adn2818 data sheet rev. e | page 24 of 40 sample phase adjust if the user is not using the ber monitor ing function, sample phase adjustment can be u s ed to optimize the horizontal samp - ling point of the incoming data eye. the adn2817 automatically centers the sampling point to the best of its ability. however, sample phase adjustment can be used to compensa te for any static phase offset of the cdr and data eye jitter profile asymmetry. sample phase adjustment is applied to the incoming eye via the phase register. the sampling phase can be adjusted by 0.5 ui, in 6 degree steps, relative to the normal cdr dat a sampling instant. using the sample phase adjustment capability uses an additional 160 mw of power. the an - 941 application note gives additional information on the use of this feature. bit error rate (ber) monitor the adn2817 has a ber measurement featur e that estimates the actual bit error rate of the ic. this feature also allows data eye jitter profiling and q - factor estimation. by knowing the ber at a sampling phase offset from the ideal sampling phase (known as pseudo ber [pber] values), it is possibl e to extrapolate to obtain an estimate of the ber at the actual sampling instant. this extrapolation relies on the assumption that the input jitter is composed of deterministic and random (gaussian) components. the implementation requires off - chip control and data processing to estimate the actual ber. a lower accuracy voltage output mode is also supported that requires no data processing or i 2 c control. brief overview of modes of operation the following two modes of operation are available for the ber feat ure: the ber extrapolation mode and the voltage output mode. only one mode can be operational at a time. the ber extra - polation mode scans the input eye in the range of 0.5 ui of the data center and reads the measured pber over the i 2 c. the user then appl ies a data processing algorithm to determine the ber. using the ber feature in this way provides for the greatest accuracy in ber estimation as the magnitude of both random (gaussian) jitter and deterministic jitter can be estimated and used to predict the actual ber. in the voltage output mode, the part autonomously samples the pber at 0.1 ui offset and decodes this value to provide an estimate of the input ber. this estimate is output via a dac as an analog current output. the an - 941 application note giv es detailed information on the use of the ber monitor features. ber extrapolation mode power saving the following three power settings are available in ber extrapolation mode: ber off, ber on, and ber standby. in ber off mode (berctlb[5] = 0) , the ber cir cuitry is powered down with the adn2817 providing normal cdr operation. in ber on mode (berctlb[5] = 1) , the internal ber circuitry is powered up. the user can perform pseudo ber measurements through the i 2 c. in ber standby mode (berctlb[5: 4] = 11 b ) , the ber is placed into a lower power mode. this setting can only be set after applying the ber on setting. these modes are defined to allow optimal power saving opportunities. it is not possible to switch between the ber off setting and the ber on setting wit hout losing lock. switching between the ber standby setting and the ber on setting is achieved without interrupting data recovery. the incremental power between the ber off setting and the ber standby setting is 77 mw and between the ber off setting and th e ber on setting it is 160 mw. ber on mode the ber on mode allows the user to scan the incoming data eye in the time dimension and build up a profile of the ber statistics. the following is a brief overview of user protocol: ? the user powers up ber circuitr y through the i 2 c. ? the user initiates the pber measurement. sample phase offset and number of data bits to be counted ( numbits is a choice among 2 18 , 2 21 , 2 24 , 2 27 , 2 30 , 2 33 , 2 36 , and 2 39 ) are supplied by the user through the i 2 c. ? the user initiates the p s eudo ber measurement by writing a 1 - to - 0 transition on berctla[3] . ? ber logic indicates the end of the ber measurement with an eobm signal and updates the number of counted errors on n um e rrors[39:0] . the user must poll the i 2 c to determine if the eobm bit, bersts[0], has been asserted. ? the user reads back n um e rrors[39:0] through the i 2 c. numerrors[39:0] is read back through the 8 - bit register ber_res at a ddr ess 0x21. the user sets berctla[2:0] to address one of the five numerrors bytes and the n reads the se lected byte from ber_res. ? pber for programmed sample phase is calculated as numerrors / numbits . ? the user initiates another pber measurement. ? the user sweeps the phase over ?0.5 ui to +0.5 ui with respect to the normal sampling instant to obtain the ber prof ile required. the adn2817 does not output the ber at the normal decision instant. it outputs pber measurements to the left and right of the normal decision instants from which the user must calculate what the ber is at the normal decision instant. a micro processor is required to parse the data and to use the remaining data for ber estimation. suitable algorithms are suggested in the an - 941 application note, ber monitor user guide .
data sheet adn2817/adn2818 rev. e | page 25 of 40 voltage output mode of operation a second mode of operation is the voltage output mode. this mode is to give easy access to a coarse estimate of the ber. the functionality is similar to that already described in the brief overview of modes of operation section except that the measure ment is performed a utonomously by the adn2817, and the result is output as a voltage on a pin from which the actual ber can be inferred. because this mode does not perform scanning of the eye to separate out deterministic jitter from random jitter effects, this method is les s accurate under normal applied jitter conditions. the user merely has to bring the bermode pin low and read the voltage on the vber pin ( see figure 32) . alternatively, a 6 - bit value can be read over the i 2 c. log (ber) vber pin voltage relative to vee (v) 0.9 0.7 0.5 0.3 0.1 vber vo lt age is guaranteed t o s a tur a te for input bers gre a ter than 0.001 vber vo lt age is guaranteed t o s a tur a te for input bers less than 0.000000001 0.001 0.00001 0.0000001 0.000000001 06001-024 figure 32 . vber vs. bit error rate squelch mode two squelch modes are available with the adn2817/adn2818: squelch dataout and clkout mode, and squelch dataout or clkout mode. squelch dataout and clkout mode is selected when ctrlc[1] = 0 (default m ode). in this mode, when the squelch input, pin 27, is driven to a ttl high state, both the clock and data outputs are set to the zero state to suppress downstream processing. if the squelch function is not required, pin 27 should b e tied to vee. squelch d ataout or clkout mode is selected when ctrlc[1] is 1. in this mode, when the squelch input is driven to a high state, the dataout pins are squelched. when the squelch input is driven to a low state, the clkout pins are squelched. this is especially useful in repeater applications, where the recovered clock may not be needed. i 2 c interface the adn2817/adn2818 support a 2 - wire, i 2 c - compatible serial bus driving multiple peripherals. two inputs, serial data (sda) and serial clock (sck), carry information bet ween any devices connected to the bus. each slave device is recognized by a unique address. the adn2817/adn2818 have two possible 7 - bit slave addresses for both read and write operations. the msb of the 7 - bit slave address is factory programmed to 1. bit 5 of the slave address is set by pin 19, saddr5. slave address bits[4:0] are defaulted to all 0s. the slave address consists of the 7 msbs of an 8 - bit word. the lsb of the word either sets a read or write operation (see figure 18 ). logic 1 corresponds to a read operation and logic 0 corresponds to a write operation. to control the device on the bus, the following protocol must be used . first, the master initiates a data transfer by establishing a start condition, defined by a high - to - low transition on sda while sck remains high. this indicates that an address/data stream follows. all peripherals respond to the start condition and shift the next eight bits (the 7 - bit address and the r/ w bit). the bits are transferred from msb to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle con dition. the idle condition is where the device monitors the sda and sck lines waiting for the start condition and correct transmitted address. the r/ w bit determines the direction of the data. logic 0 on the lsb of the first byte means th at the master writes information to the peripheral. logic 1 on the lsb of the first byte means that the master reads information from the peripheral. the adn2817/adn2818 act as standard slave devices on the bus. the data on the sda pin is eight bits long , supporting the 7 - bit addresses plus the r/ w bit. the adn2817/adn2818 have eight subaddresses to enable the user - accessible internal registers (see table 8 through tabl e 16 ). it, therefore , interprets the first byte as the device address and the second byte as the starting subaddress. auto - increment mode is supported, allowing data to be read from, or written to, the starting subaddress and each subsequent address without manually addressin g the subsequent subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one - by - one basis without updating all registers. stop and start conditions can be detected at any stage of t he data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given sck high period, the user should issue one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the adn2817/adn2818 do not issue an acknowledge and return to the idle condition.
adn2817/adn2818 data sheet rev. e | page 26 of 40 if the user exceeds the highest subaddress while reading back in auto-increment mode, the highest subaddress register contents continue to be output until the master device issues a no acknowl- edge. this indicates the end of a read. in a no acknowledge condition, the sda line is not pulled low on the ninth pulse. see figure 19 and figure 20 for sample read and write data transfers and figure 21 for a more detailed timing diagram. reference clock (optional) a reference clock is not required to perform clock and data recovery with the adn2817/adn2818. however, support for an optional reference clock is provided. the reference clock can be driven differentially or single-ended. if the reference clock is not used, tie refclkp to vcc, and either leave refclkn floating or tie it to vee (the inputs are internally terminated to vcc/2). see figure 33 through figure 35 for sample configurations. the refclk input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mv (for example, lvpecl or lvds) or a standard single-ended low voltage ttl input, providing maximum system flexibility. phase noise and duty cycle of the reference clock are not critical and 100 ppm accuracy is sufficient. buffer 100k ? 100k ? vcc/2 10 11 refclkn refclkp adn2817/adn2818 06001-021 figure 33. differential refclk configuration buffer 100k ? 100k ? vcc/2 10 11 refclkn refclkp adn2817/adn2818 clk osc out vcc 06001-022 figure 34. single-ended refclk configuration buffer 100k ? 100k ? vcc/2 10 11 refclkn refclkp a dn2817/adn2818 v cc 06001-023 figure 35. no refc lk configuration the two uses of the reference clock are mutually exclusive. the reference clock can be used either as an acquisition aid for the adn2817/adn2818 to lock onto data, or to measure the fre- quency of the incoming data to within 0.01%. (there is the capability to measure the data rate to approximately 10% without the use of a reference clock.) the modes are mutually exclusive because, in the first use, the user knows exactly what the data rate is and wants to force the part to lock onto only that data rate; in the second use, the user does not know what the data rate is and wants to measure it. lock to reference mode is enabled by writing 1 to i 2 c register bit ctrla[0]. data rate readback mode is enabled by writing 1 to i 2 c register bit ctrla[1]. writing a 1 to both of these bits at the same time causes an indeterminate state and is not supported. using the reference clock to lock onto data writing ctrla[0] = 1 puts the adn2817/adn2818 into lock to refclk (ltr) mode. in this mode, the adn2817/adn2818 lock onto a frequency derived from the reference clock according to the following equation: data rate /2 ctrla[5:2] = refclk /2 ctrla[7:6] the user must know exactly what the data rate is and provide a reference clock that is a function of this rate. the adn2817/ adn2818 can still be used as continuous rate devices in this configuration if a reference clock with a variable frequency is provided (see the an-632 application note). the reference clock can be anywhere between 10 mhz and 200 mhz. by default, the adn2817/adn2818 expect a reference clock of between 10 mhz and 25 mhz. if it is between 25 mhz and 50 mhz, 50 mhz and 100 mhz, or 100 mhz and 200 mhz, the user needs to configure the adn2817/adn2818 to use the correct reference frequency range by setting two bits of the ctrla register, ctrla[7:6]. table 17. ctrla[7:6] (f ref range) with ctrla[5:2] (div_fref ratio) settings ctrla[7:6] range (mhz) ctrla[5:2] ratio 00 10 to 25 0000 1 01 25 to 50 0001 2 10 50 to 100 n 2 n 11 100 to 200 1000 256
data sheet adn2817/adn2818 rev. e | page 27 of 40 the user can specify a fixed integer multiple of the reference clock to lock onto using ctrla[5:2], where ctrla should be set to the data rate/div_fref and div_fref represents the divided - down reference referred to the 10 mhz to 25 mhz band. for example, if the reference clock frequency is 38.88 mhz and the input data rate is 622.08 m bps, then ctrla[7:6] is set to 01 to give a divided - down reference clock of 19.44 mhz. ctrla[5:2] is set to 0101, that is, 5, because 622.08 mbps/19.44 mhz = 2 5 when the ctrla[7:2] value is correct and ctrla[0] has been written to a logic 1, it is recommended that a 1 - to - 0 transition be written to ctrlb[5] to initiate a new frequency acquisition with respect to the reference clock. in this mode, if the adn2817/adn2818 lose lock for any reason, they relock onto the reference clock and continue to output a stable clock. though the adn2817/adn2818 operate in ltr mode, if the user ever changes the reference frequency, the f ref range (ctrla[7:6]), or the div_fref ratio (ctrla[5:2]), this must be followe d by writing a 1 - to - 0 transition into the ctrlb[5] bit to initiate a new frequency acquisition. a frequency acquisition can also be initiated in ltr mode by writing a 0 - to - 1 transition into ctrla[0]; however, it is rec - ommended that a frequency acquisitio n be initiated by writing a 1 - to - 0 transition into ctrlb[5] , as explained previously. using the reference clock to measure data frequency the user can also provide a reference clock to measure the recovered data frequency. in this case, the user provides a reference clock, and the adn2817/adn2818 compare the frequency of the incoming data to the incoming reference clock and return a ratio of the two frequencies to 0.01% (100 ppm). the accuracy error of the reference clock is added to the accuracy of the ad n2817/adn2818 data rate measurement. for example, if a 100 ppm accuracy reference clock is used, the total accuracy of the measurement is within 200 ppm. the reference clock can range from 10 mhz to 200 mhz. the adn2817/adn2818 expects a reference clock be tween 10 mhz and 25 mhz by default. if it is between 25 mhz and 50 mhz, 50 mhz and 100 mhz, or 100 mhz and 200 mhz, the user needs to configure the adn2817/adn2818 to use the correct reference frequency range by setting two bits of the ctrla register, ctrl a[7:6]. using the reference clock to determine the frequency of the incoming data does not affect the manner in which the part locks onto data. in this mode, the reference clock is used only to determine the frequency of the data. for this reason, the user does not need to know the data rate to use the reference clock in this manner. prior to reading back the data rate using the reference clock, the ctrla[7:6] bits must be set to the appropriate frequency range with respect to the reference clock being use d. a fine data rate readback is then executed as follows: 1. wr ite a 1 to ctrla[1]. this enables the fine data rate measurement capability of the adn2817/adn2818. this bit is level sensitive and does not need to be reset to perform subsequent frequency meas urements. 2. reset misc [2] by writing a 1 followed by a 0 to ctrlb[3]. this initiates a new data rate measurement. 3. read back misc[2]. if it is 0, the measurement is not complete. if it is 1, the measurement is complete and the data rate can be read back on f req[22:0]. the time for a data rate measurement is typically 80 ms. 4. read back the data rate from the freq2[6:0], freq1[7:0], and freq0[7:0] registers. use the following equation to determine the data rate: f datarate = ( freq [ 22..0 ] f refclk ) /2 (14 + sel_rat e ) (1) where: freq[22:0] is the reading from freq2[6:0] (most significant byte), freq1[7:0], and freq0[7:0] (least significant byte). see table 18. f datarate is the data rate (mbps). f refclk is the refclk frequency (mhz). sel_rate is the setting from ctrla[7:6]. table 18. d22 d21 : d17 d16 d15 d14 : d9 d8 d7 d6: d1 d0 freq2[6:0] freq1[7:0] freq0[7:0] for example, if the reference clock frequency is 32 mhz, it falls within the 25 mhz to 50 mhz range; theref ore, the ctrla[7:6] setting is 01 resulting in sel_rate = 1. for this example, the input data rate is 2.488 gbps (oc - 48). after following step 1 through step 4, the value that is read back on freq[22:0] = 0x26e010, which is equal to 2.5477 10 6 . plugging this value into equation 1 yields ((2.5477 10 6 ) (32 10 6 ))/(2 (14 + 1) ) = 2.488 gbps if subsequent frequency measurements are required, ctrla[1] should remain set to 1. it does not need to be reset. the measure - ment process is reset by writing a 1 followed by a 0 to ctrlb[3]. this initiates a new data rate measurement. follow step 2 through step 4 to read back the new data rate. note that a data rate readback is valid only if lol is low. if lol is high, the data rate readback is invalid.
adn2817/adn2818 data sheet rev. e | page 28 of 40 additional featu res available via th e i 2 c interface coarse data rate readback the data rate can be read back over the i 2 c interface to approximately 10% without needing an external reference clock. a 9 - bit register, coarse_rd[8:0], can be read back when lol is deassert ed. the eight msbs of this register are the contents of the rate [7:0] register. the lsb of the coarse_rd register is bit misc[0]. table 19 is a look - up table (lut) that provides coarse data rate readback values to within 10%. lo s configuration the los detector output, p in 22 (los) , can be configured as either active high or active low. if ctrlc[2] is set to logic 0 (default), the los pin is active high when a loss of signal condition is detected. writing a 1 to ctrlc[2] configur es the los pin to be active low when a loss of signal condition is detected. initiate frequency acquisition a frequency acquisition can be initiated by writing a 1 followed by a 0 to the i 2 c register bit ctrlb[5]. this initiates a new frequency acquisiti on while keeping the adn2817/adn2818 in the operating mode that was previously programmed in the ctrla, ctrlb, ctrlc, ctrld, and ctrle registers. rate selectivity the adn2817/adn2818 can operate in a limited range mode in situations where the user wants to restrict the data rates to which the device can lock. in this mode, the frequency acquisition range of the device is limited to a specific range of data rates. the acquisition range is determined by program ming an upper and lower 9 - bit code into the hi_c ode[8:1], lo_code[8:1], and code_lsb[1:0] i 2 c registers. see table 20 for a look - up table (lut) showing the correct register settings for each data rate. table 20 has three columns: code, high limit, and low limit. the user programs the code value for the high limit data rate into hi_code and the code value for the low limit data rate into lo_code to set the appropriate range. for example, if the user wants to limit the acquisition range of the adn2817/ad n2818 to lock between 1 gbps and 1.25 gbps , the following steps must be taken: 1. find the first code in table 20 that corresponds to a data r ate below 1.0 gbps in the low limit column, that is, code 236 or 011101100b. set lo_code[8: 1] = 01110110b (lo_code[0] is set in register bit code_lsb[0].) 2. find the first code in table 20 that corresponds to a data rate above 1.25 gbps in the high limit column, that is, code 258 or 100000010b. set hi_code[8:1] = 10000001 b (hi_code[0] is set in register bit code_lsb[1].) 3. set code_lsb = 00000000b given that the hi_code[0] = 0 and lo_code[0] = 0. 4. set sel_mode[3] = 1. 5. when there is a valid input to the device between 1.0 gbps and 1.25 gbps, write a 1 - to - 0 transition into ctrl b[5] to initiate a new frequency acquisition . double data rate mode setting ctrle = 0x02 puts the adn2817/adn2818 clock output through divide - by - two circuitry allowing direct interfacing to fpgas that support data clocking on both rising and falling edges . prbs generator/detector the adn2817/adn2818 have an integrated prbs generator/ detector for system testing purposes. the devices are configurable as either a prbs detector or a prbs generator. the two functions cannot be used at the same time. the foll owing steps configure the prbs detector (prbs 7 only): 1. set ctrle [2:0] = 0x5. 2. set ctrld[2:0] = 0x4 to enable the prbs detector. the prbs error signal outputs on the dataoutp/dataoutn pins. every time the prbs detector detects an error, the dataoutp/dataoutn outputs pulse twice to a logic 1, that is, dataoutp = 1, dataoutn = 0. the following steps configure the prbs generator (prbs 7 only): 1. set ctrle[2:0] = 0x5. 2. set ctrld[2:0] = 0x1 to enable the prbs generator. 3. wr ite a 1 - to - 0 transition into ctrld[3] to ini tiate a prbs 7 pattern. note that the prbs generator is clocked by the vco; therefore, the user needs to feed in a clock at half the desired frequency. for example, for an oc - 48 prbs pattern, input a 1.244 ghz clock to pin/nin. this appears as a 2.488 gbps nrz data pattern to the adn2817/adn2818. the recovered clock is 2.488 ghz, which clocks the prbs generator to produce an oc - 48 prbs pattern on the outputs.
data sheet adn2817/adn2818 rev. e | page 29 of 40 clk holdover mode this mode of operation is available in ltd mode. in clk holdover mode, the out put clock frequency remains within 5% if the input data is removed or changed. to operate in this mode, the user writes to the i 2 c to put the part into clk holdover mode by setting sel_mode[1] = 1. the user must then initiate a frequency acquisition by writing a 1 - to - 0 transi - tion into ctrlb[5], at which time the device locks onto the input data rate. at this point, the output frequency remains within 5% of the initial acquired value regardless of whether the input data is removed or the data rate chang es. it is important to note that all frequency acquisitions in this mode must be initiated by writing a 1 - to - 0 transition into ctrlb[5]. in this mode, the device does not automatically initiate a new frequency acquisition when the input is momen - tarily in terrupted or if the input data rate changes. cdr bypass mode the cdr on the adn2817/adn2818 can be bypassed by setting bit ctrld[7] = 1. in this mode, the adn2817/adn2818 feed the input directly through the input amplifiers to the output buffer, completely bypassing the cdr. disable output buffers the adn2817/adn2818 provide the option of disabling the output buffers for power savings. the clock output buffers can be disabled by setting bit ctrld[5] = 1. this reduces the total power consumption of the dev ice by ~100 mw. for an additional 100 mw power savings, such as in low power standby mode, the data output buffers can also be disabled by setting bit ctrld[6] = 1.
adn2817/adn2818 data sheet rev. e | page 30 of 40 applications informa tion pcb design guideline s proper rf pcb design techniques must be used for optimal performance. power supply connections and ground planes for best practice, the use of one low impedance ground plane is recommended. to reduce series inductance, solder the vee pins directly to the ground plane. if the ground plane is an i nternal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance, especially on pin 23, which is the ground return for the output buffers. connect the exposed pad to the ground p lane using plugged vias so that solder does not leak through the vias during reflow. use of a 10 f electrolytic capacitor between vcc and vee is recommended at the location where the 3.3 v supply enters the pcb. when using 0.1 f and 1 nf ceramic chip ca pacitors, they should be placed between the ic power supply (vcc and vee), as close as possible to the adn2817/adn2818 vcc pins. if connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series in ductance, especially on pin 24, which supplies power to the high speed clkoutp/clkoutn and dataoutp/dataoutn outp ut buffers. see the schematic in figure 36 for recommended connections. by using adjacent power supply and ground plan es, excellent high frequency decoupling can be realized by using close spacing between the planes. this capacitance is given by c plane = 0.88 r a/d (pf) where: r is the dielectric constant of the pcb material. a is the area of the overlap of power and gr ound planes (cm 2 ). d is the separation between planes (mm). for fr - 4, r = 4.4 and 0.25 mm spacing, c 15 pf/cm 2 . vber 32 vcc 31 vee 30 dataoutp 29 dataoutn 28 squelch 27 clkoutp 26 clkoutn 25 thradj r th 9 refclkp 10 refclkn 11 vcc 12 vee 13 cf2 14 cf1 15 lol 16 bermode 1 vcc 2 vref 3 nin 4 pin 5 slicep 6 slicen 7 vee 8 vcc 24 vee 23 los 22 sda 21 sck exposed pad tied off to vee plane with vias. 20 saddr5 19 vcc 18 vee 17 adn2817/ adn2818 top view (not to scale) 1nf 0.1f vcc 0.47f +20% !0? insul a tion resis t ance c i 2 c controller c vcc vcc 1nf 0.1f 1nf 0.1f c in vcc tia ? ? 1nf 0.1f 0.1f dataoutp dataoutn clkoutp clkoutn ?75$160,66,21 lines vcc ?? 1nf 0.1f + vcc 10f 06001-025 10k ? 10k ? figure 36 . typical adn2817/adn2818 applications circuit
data sheet adn2817/adn2818 rev. e | page 31 of 40 transmission lines use of 50 transmission lines is required for all high frequency input and output signals to minimize reflections: pin, nin, clkoutp, clkoutn, dataoutp, and dataoutn (also refclkp, refclkn, if using a high frequency reference clock, such as 155 mhz). it is also necessary for the pin/nin input traces to be matched in length, and the clkoutp, clkoutn, dataoutp, and dataoutn output traces to be matched in length to avoid skew between the differential traces. all high speed cml outputs (clkoutp, clkoutn, dataoutp, and dataoutn) require 100 back termination chip resis- tors connected between the output pin and vcc. place these resistors as close as possible to the output pins. these 100 resistors are in parallel with on-chip 100 termination resistors to create a 50 back termination (see figure 37). the high speed inputs (pin and nin) are internally terminated with 50 to an internal reference voltage (see figure 38). a 0.1 f capacitor is recommended between vref, pin 3, and gnd to provide an ac ground for the inputs. as with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes. 50? 50? v term v term 50? 0.1f 0.1f 100? 100? vcc 100? 100? vcc adn2817/ adn2818 0 6001-026 figure 37. typical adn2817/adn2818 applications circuit 50? 50? 50? 2.5v adn2817/adn2818 vcc tia c in c in pin nin 3k ? vref 0.1f tia 06001-027 figure 38. adn2817/adn2818 ac-coupled input configuration soldering guidelines for lead frame chip scale package the lands on the 32-lead lfcsp are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. center the land on the pad to ensure that the solder joint size is maximized. the bottom of the lead frame chip scale package has a central exposed pad. the pad on the printed circuit board should be at least as large as this exposed pad. the user must connect the exposed pad to vee using plugged vias to prevent solder from leaking through the vias during reflow. this ensures a solid connection from the exposed pad to vee. choosing ac coupling capacitors ac coupling capacitors at the input (pin, nin) and output (dataoutp, dataoutn) of the adn2817/adn2818 must be chosen such that the device works properly over the full range of data rates used in the application. when choosing the capacitors, the time constant formed with the two 50 resistors in the signal path must be considered. when a large number of consecutive identical digits (cids) are applied, the capacitor voltage can droop due to baseline wander (see figure 39), causing pattern dependent jitter (pdj). the user must determine how much droop is tolerable and choose an ac coupling capacitor based on that amount of droop. the amount of pdj can then be approximated based on the capacitor selection. the actual capacitor value selection may require some trade-offs between droop and pdj. for example, assuming that 2% droop can be tolerated, the maximum differential droop is 4%. normalizing to peak-to- peak voltage, droop = v = 0.04 v = 0.5 v p-p (1 ? e Ct/ ) ; therefore, = 12 t where: is the rc time constant (c is the ac coupling capacitor, and r = 100 seen by c). t is the total discharge time, which is equal to n ? . n is the number of cids. t is the bit period. calculate the capacitor value by combining the equations for and t. c = 12nt/r when the capacitor value is selected, the pdj can be approximated as pdj ps p-p = 0.5 t r (1 ? e (?nt/rc ) )/0.6 where: pdj ps p-p is the amount of pattern-dependent jitter allowed; <0.01 ui p-p typical. t r is the rise time, which is equal to 0.22/ bw , where bw 0.7 (bit rate). note that this expression for t r is accurate only for the inputs. the output rise time for the adn2817/adn2818 is ~100 ps regardless of data rate.
adn2817/adn2818 data sheet rev. e | page 32 of 40 notes 1. during the data patterns with high transition density, differential dc voltage at v1 and v2 is zero. 2. when the output of the tia goes to cid, v1 and v1b are driven to different dc levels. v2 and v2b discharge to the vref level which effectively introduces a differential dc offset across the ac coupling capacitors. 3. when the burst of data starts again, the differential dc offset across the ac coupling capacitors is applied to the input levels causing a dc shift in the differential input. this shift is large enough such that one of the states, either high or low depending on the levels of v1 and v1b when the tia went to cid, is cancelled out. the quantizer does not recognize this as a valid state. 4. the dc offset slowly discharges until the differential input voltage exceeds the sensitivity of the adn2817. the quantizer recognizes both high and low states at this point. v1 v1b v2 v2b vdiff vdiff = v2 ? v2b vth = adn2817 quantizer threshold 2 34 1 vref vth cdr limamp v ref 50 ? 50 ? pin nin adn2817 c out dataoutp dataoutn c in v2 v2b v1 v1b tia v cc 06001-028 figure 39. example of baseline wander dc-coupled application the inputs to the adn2817/adn2818 can also be dc-coupled. this can be necessary in burst mode applications with long periods of cids and where baseline wander cannot be tolerated. if the inputs to the adn2817/adn2818 are dc-coupled, care must be taken not to violate the input range and common-mode level requirements of the adn2817/adn2818 (see figure 40 through figure 42). if dc coupling is required, and the output levels of the tia do not adhere to the levels shown in figure 41, level shifting and/or attenuation must occur between the tia outputs and the adn2817/adn2818 inputs. 50? 50? 50 ? 2.5v adn2817/adn2818 vcc tia pin nin 3k? vref 0.1f tia 06001-029 figure 40. dc-cou pled application pin input (v) v p-p = pin ? nin = 2 v se = 10mv at sensitivity v se = 5mv min v cm = 2.3v min (dc-coupled) nin 06001-030 figure 41. minimum allowed dc-coupled input levels pin input (v) v p-p = pin ? nin = 2 v se = 2.0v max v se = 1.0v max v cm = 2.3v (dc-coupled) nin 06001-031 figure 42. maximum allowed dc-coupled input levels
data sheet adn2817/adn2818 rev. e | page 33 of 40 coarse data rate rea dback look - up table code is the 9 - bit value read back from coarse_rd[8:0]. table 19 . coarse data rate readback look- up table code f mid (hz) 0 5.3205 10 6 1 5.3202 10 6 2 5.4294 10 6 3 5.5473 10 6 4 5.6735 10 6 5 5.8086 10 6 6 5.9533 10 6 7 6.1087 10 6 8 6.2771 10 6 9 6.4716 10 6 10 6.6702 10 6 11 6.8884 10 6 12 7.1269 10 6 13 7.3889 10 6 14 7.6789 10 6 15 7.9990 10 6 16 7.6264 10 6 17 7.6263 10 6 18 7.7893 10 6 19 7.9650 10 6 20 8.1539 10 6 21 8.3566 10 6 22 8.5749 10 6 23 8.810 3 10 6 24 9.0650 10 6 25 9.3584 10 6 26 9.6606 10 6 27 9.9906 10 6 28 10.3514 10 6 29 10.7475 10 6 30 11.1821 10 6 31 11.6571 10 6 32 10.6409 10 6 33 10.6403 10 6 34 10.8588 10 6 35 11.0945 10 6 36 11.3469 10 6 37 11.6173 10 6 38 11.9065 10 6 39 12.2174 10 6 40 12.5543 10 6 41 12.9432 10 6 42 13.3403 10 6 43 13.7767 10 6 44 14.2539 10 6 45 14.7778 10 6 46 15.3577 10 6 47 15.9980 10 6 48 15.2529 10 6 code f mid (hz) 49 15.2526 10 6 50 15.5785 10 6 51 15.9300 10 6 52 16.3078 10 6 53 16.7133 10 6 54 17.1498 10 6 55 17.6205 10 6 56 18.1300 10 6 57 18.7169 10 6 58 19.3212 10 6 59 19.9811 10 6 60 20.7027 10 6 61 21.4950 10 6 62 22.3642 10 6 63 23.3143 10 6 64 21.2818 10 6 65 21.2806 10 6 66 21.7177 10 6 67 22.1891 10 6 68 22.6939 10 6 69 23.2346 10 6 70 23.8130 10 6 71 24.4348 10 6 72 25.1085 10 6 73 25.8864 10 6 74 26.6807 10 6 75 27.5535 10 6 76 28.5078 10 6 77 29.5555 10 6 78 30.7155 10 6 79 31.9959 10 6 80 30.5057 10 6 81 30.5052 10 6 82 31.1570 10 6 83 31.8599 10 6 84 32.6155 10 6 85 33.4265 10 6 86 34.2996 10 6 87 35.2411 10 6 88 36.2600 10 6 89 37.4338 10 6 90 38.6424 10 6 91 39.9623 10 6 92 41.4055 10 6 93 42.9900 10 6 94 44.7284 10 6 95 46.6285 10 6 96 42.5637 10 6 97 42.5613 10 6 code f mid (hz) 98 43.4353 10 6 99 44.3782 10 6 100 45.3877 10 6 101 46.4691 10 6 102 47.6260 10 6 103 48.8696 10 6 104 50.2170 10 6 105 51.7728 10 6 106 53.3614 10 6 107 55.1069 10 6 108 57.0156 10 6 109 59.1111 10 6 110 61.4309 10 6 111 63.9919 10 6 112 61.0114 10 6 113 61.0103 10 6 114 62.3141 10 6 115 63.7198 10 6 116 65.2310 10 6 117 66.8530 10 6 118 68.5992 10 6 119 70.4821 10 6 120 72.5199 10 6 121 74.8675 10 6 122 77.2849 10 6 123 79.9245 10 6 124 82.8109 10 6 125 85.9801 10 6 126 89.4567 10 6 127 93.2571 10 6 128 85.1274 10 6 129 85.1226 10 6 130 86.8707 10 6 131 88.7564 10 6 132 90.7755 10 6 133 92.9383 10 6 134 95.2521 10 6 135 97.7392 10 6 136 100.4340 10 6 137 103.5457 10 6 138 106.7228 10 6 139 110.2139 10 6 140 114.0312 10 6 141 118.2222 10 6 142 122.8619 10 6 143 127.9838 10 6 144 122.0229 10 6 145 122.0206 10 6 146 124.6282 10 6 code f mid (hz) 147 127.4396 10 6 148 130 .4620 10 6 149 133.7061 10 6 150 137.1983 10 6 151 140.9643 10 6 152 145.0399 10 6 153 149.7350 10 6 154 154.5698 10 6 155 159.8491 10 6 156 165.6218 10 6 157 171.9601 10 6 158 178.9134 10 6 159 186.5142 10 6 160 170.2547 10 6 161 170.2451 10 6 162 173.7413 10 6 163 177.5128 10 6 164 181.5509 10 6 165 185.8765 10 6 166 190.5041 10 6 167 195.4784 10 6 168 200.8681 10 6 169 207.0913 10 6 170 213.4455 10 6 171 220.4277 10 6 172 228.0624 10 6 173 236.4443 10 6 174 245.7237 10 6 175 255.9676 10 6 176 244.0458 10 6 177 244.0412 10 6 178 249.2563 10 6 179 254.8792 10 6 180 260.9240 10 6 181 267.4122 10 6 182 274.3966 10 6 183 281.9286 10 6 184 290.0798 10 6 185 299.4700 10 6 186 309.1396 10 6 187 319.6981 10 6 188 331.2437 10 6 189 343.9202 10 6 190 357.8269 10 6 191 373.0284 10 6 192 340.5094 10 6 193 340.4903 10 6 194 347.4826 10 6 195 355.0256 10 6
adn2817/adn2818 data sheet rev. e | page 34 of 40 code f mid (hz) 196 363.1019 10 6 197 371.7531 10 6 198 381.0083 10 6 199 390.9568 10 6 200 401.7362 10 6 201 414.1826 10 6 202 426.8911 10 6 203 440.8554 10 6 204 456.1247 10 6 205 472.8887 10 6 206 491.4474 10 6 207 511.9351 10 6 208 488.0916 10 6 209 488.0824 10 6 210 498.5126 10 6 211 509.7584 10 6 212 521.8480 10 6 213 534.8244 10 6 214 548.7933 10 6 215 563.8571 10 6 216 580.1596 10 6 217 598.9401 10 6 218 618.2792 10 6 code f mid (hz) 219 639.3962 10 6 220 662.4874 10 6 221 687.8404 10 6 222 715.6537 10 6 223 746.0568 10 6 224 681.0188 10 6 225 680.9806 10 6 226 694.9652 10 6 227 710.0511 10 6 228 726.2037 10 6 229 743.5062 10 6 230 762.0166 10 6 231 781.9136 10 6 232 803.4724 10 6 233 828.3653 10 6 234 853.7822 10 6 235 881.7109 10 6 236 912.2494 10 6 237 945.7774 10 6 238 982.8948 10 6 239 1.0239 10 9 240 976.1832 10 6 241 976.1648 10 6 code f mid (hz) 242 997.0253 10 6 243 1.0195 10 9 244 1.0437 10 9 245 1.0696 10 9 246 1.0976 10 9 247 1.1277 10 9 248 1.1603 10 9 249 1.1979 10 9 250 1.2366 10 9 251 1.2788 10 9 252 1.3250 10 9 253 1.3757 10 9 254 1.4313 10 9 255 1.4921 10 9 256 1.3620 10 9 257 1.3620 10 9 258 1.3899 10 9 259 1.4201 10 9 260 1.4524 10 9 261 1.4870 10 9 262 1.5240 10 9 263 1.5638 10 9 264 1.6069 10 9 code f mid (hz) 265 1.6567 10 9 266 1.7076 10 9 267 1.7634 10 9 268 1.8245 10 9 269 1.8916 10 9 270 1.9658 10 9 271 2.0477 10 9 272 1.9524 10 9 273 1.9523 10 9 274 1.9941 10 9 275 2.0390 10 9 276 2.0874 10 9 277 2.1393 10 9 278 2.1952 10 9 279 2.2554 10 9 280 2.3206 10 9 281 2.3958 10 9 282 2.4731 10 9 283 2.5576 10 9 284 2.6499 10 9 285 2.7514 10 9 286 2.8626 10 9 287 2.9842 10 9
data sheet adn2817/adn2818 rev. e | page 35 of 40 hi_code and lo_code look - up table code is the 9 - bit value to be written into hi_code[8:0] and lo_code[8:0]. use t he high limit code for hi_code and the low limit code for lo_code. table 20. code low limit high limit 0 5.7633 10 6 4.8677 10 6 1 5.7631 10 6 4.8674 10 6 2 5.8777 10 6 4.9708 10 6 3 6.0011 10 6 5.0827 10 6 4 6.1328 10 6 5.2027 10 6 5 6.2738 10 6 5.3312 10 6 6 6.4245 10 6 5.4692 10 6 7 6.5859 10 6 5.6188 10 6 8 6.7593 10 6 5.7807 10 6 9 6.9599 10 6 5.9680 10 6 10 7.1641 10 6 6.1614 10 6 11 7.3860 10 6 6.3740 10 6 12 7.6292 10 6 6.6070 10 6 13 7.8947 10 6 6.8660 10 6 14 8.1855 10 6 7.1541 10 6 15 8.5061 10 6 7.4742 10 6 16 8.2705 10 6 6.9705 10 6 17 8.2701 10 6 6.9703 10 6 18 8.4414 10 6 7.1241 10 6 19 8.6260 10 6 7.2904 10 6 20 8.8239 10 6 7.4696 10 6 21 9.0356 10 6 7.6624 10 6 22 9.2629 10 6 7.8705 10 6 23 9.5073 10 6 8.0958 10 6 24 9.7707 10 6 8.3404 10 6 25 10.0733 10 6 8.6236 10 6 26 10.3832 10 6 8.9165 10 6 27 10.7202 10 6 9.2377 10 6 28 11.0869 10 6 9.5915 10 6 29 11.4873 10 6 9.9825 10 6 30 11.9244 10 6 10.4145 10 6 31 12.3996 10 6 10.8902 10 6 32 11.5265 10 6 9.7355 10 6 33 11.5261 10 6 9.7347 10 6 34 11.7554 10 6 9.9415 10 6 35 12.0022 10 6 10.1654 10 6 36 12.2655 10 6 10.4053 10 6 37 12.5475 10 6 10.6624 10 6 38 12.8490 10 6 10.9384 10 6 39 13.1718 10 6 11.2376 10 6 40 13.5186 10 6 11.5615 10 6 41 13.9198 10 6 11.9360 10 6 42 14.3282 10 6 12.3228 10 6 43 14.7719 10 6 12.7480 10 6 44 15.2584 10 6 13.2140 10 6 45 15.7894 10 6 13.7321 10 6 46 16.3711 10 6 14.3081 10 6 47 17.0122 10 6 14.9484 10 6 code low limit high limit 48 16.5410 10 6 13.9411 10 6 49 16.5402 10 6 13.9407 10 6 50 16.8827 10 6 14.2483 10 6 51 17.2521 10 6 14.5807 10 6 52 17.6479 10 6 14.9392 10 6 53 18.0712 10 6 15.3247 10 6 54 18.5258 10 6 15.7411 10 6 55 19.0145 10 6 16.1915 10 6 56 19.5415 10 6 16.6807 10 6 57 20.1465 10 6 17.2471 10 6 58 20.7665 10 6 17.8330 10 6 59 21.4403 10 6 18.4754 10 6 60 22.1738 10 6 19.1829 10 6 61 22.9747 10 6 19.9651 10 6 62 23.8487 10 6 20.8291 10 6 63 24.7993 10 6 21.7805 10 6 64 23.0530 10 6 19.4710 10 6 65 23.0523 10 6 19.4695 10 6 66 23.5108 10 6 19.8831 10 6 67 24.0044 10 6 20.3308 10 6 68 24.5310 10 6 20.8107 10 6 69 25.0951 10 6 21.3248 10 6 7 0 25.6980 10 6 21.8768 10 6 71 26.3436 10 6 22.4751 10 6 72 27.0373 10 6 23.1230 10 6 73 27.8396 10 6 23.8720 10 6 74 28.6564 10 6 24.6457 10 6 75 29.5438 10 6 25.4960 10 6 76 30.5167 10 6 26.4281 10 6 77 31.5787 10 6 27.4641 10 6 78 32.7422 10 6 28.6162 10 6 79 34.0244 10 6 29.8968 10 6 80 33.0819 10 6 27.8821 10 6 81 33.0805 10 6 27.8813 10 6 82 33.7655 10 6 28.4965 10 6 83 34.5041 10 6 29.1615 10 6 84 35.2957 10 6 29.8783 10 6 85 36.1424 10 6 30.6494 10 6 86 37.0517 10 6 31.4822 10 6 87 38.0290 10 6 32.3831 10 6 88 39.0830 10 6 33.3615 10 6 89 40.2930 10 6 34.4942 10 6 90 41.5329 10 6 35.6659 10 6 91 42.8807 10 6 36.9508 10 6 92 44.3477 10 6 38.3658 10 6 93 45.9493 10 6 39.9301 10 6 94 47.6975 10 6 41.6582 10 6 95 49.5986 10 6 43.5610 10 6
adn2817/adn2818 data sheet rev. e | page 36 of 40 code low limit high limit 96 46.1061 10 6 38.9419 10 6 97 46.1045 10 6 38.9390 10 6 98 47.0217 10 6 39.7661 10 6 99 48.0087 10 6 40.6617 10 6 100 49.0620 10 6 41.6214 10 6 101 50.1902 10 6 42.6496 10 6 102 51.3960 10 6 43.7535 10 6 103 52.6872 10 6 44.9502 10 6 104 54.0746 10 6 46.2459 10 6 105 55.6792 10 6 47.7440 10 6 106 57.3128 10 6 49.2913 10 6 107 59.0876 10 6 50.9920 10 6 108 61.0334 10 6 52.8561 10 6 109 63.1575 10 6 54.9282 10 6 110 65.4843 10 6 57.2324 10 6 111 68.0487 10 6 59.7936 10 6 112 66.1639 10 6 55.7643 10 6 113 66.1609 10 6 55.7626 10 6 114 67.5309 10 6 56.9931 10 6 115 69.0082 10 6 58.3229 10 6 116 70.5914 10 6 59.7566 10 6 117 72.2848 10 6 61.2989 10 6 118 74.1034 10 6 62.9643 10 6 119 76.0580 10 6 64.7662 10 6 120 78.1660 10 6 66.7230 10 6 121 80.5861 10 6 68.9885 10 6 122 83.0658 10 6 71.3318 10 6 123 85.7613 10 6 73.9016 10 6 124 88.6953 10 6 76.7317 10 6 125 91.8987 10 6 79.8603 10 6 126 95.3950 10 6 83.3164 10 6 127 99.1972 10 6 87.1220 10 6 128 92.2121 10 6 77.8839 10 6 129 92.2090 10 6 77.8780 10 6 130 94.0434 10 6 79.5323 10 6 131 96.0174 10 6 81.3234 10 6 132 98.1240 10 6 83.2427 10 6 133 100.3804 10 6 85.2993 10 6 134 102.7920 10 6 87.5071 10 6 135 105.3744 10 6 89.9004 10 6 136 108.1491 10 6 92.4919 10 6 137 111.3583 10 6 95.4879 10 6 138 114.6257 10 6 98.5827 10 6 139 118.1753 10 6 101.9841 10 6 140 122.0668 10 6 105.7122 10 6 141 126.3150 10 6 109.8565 10 6 142 130.9686 10 6 114.4648 10 6 143 136.0974 10 6 119.5872 10 6 144 132.3278 10 6 111.5286 10 6 145 132.3218 10 6 111.5252 10 6 146 135.0619 10 6 113.9862 10 6 147 138.0164 10 6 116.6459 10 6 148 141.1829 10 6 119.5132 10 6 code low limit high limit 149 144.5697 10 6 122.5977 10 6 150 148.2068 10 6 125.9286 10 6 151 152.1160 10 6 129.5324 10 6 152 156.3320 10 6 133.4459 10 6 153 161.1721 10 6 137.9770 10 6 154 166.1317 10 6 142.6637 10 6 155 171.5227 10 6 147.8032 10 6 156 177.3906 10 6 153.4634 10 6 157 183.7974 10 6 159.7205 10 6 158 190.7899 10 6 166.6328 10 6 159 198.3944 10 6 174.2440 10 6 160 184.4242 10 6 155.7678 10 6 161 184.4181 10 6 155.7560 10 6 162 188.0868 10 6 159.0645 10 6 163 192.0348 10 6 162.6467 10 6 164 196.2480 10 6 166.4855 10 6 165 200.7608 10 6 170.5985 10 6 166 205.5841 10 6 175.0142 10 6 167 210.7488 10 6 179.8008 10 6 168 216.2983 10 6 184.9838 10 6 169 222.7166 10 6 190.9759 10 6 170 229.2514 10 6 197.1654 10 6 171 236.3506 10 6 203.9681 10 6 172 244.1336 10 6 211.4245 10 6 173 252.6300 10 6 219.7129 10 6 174 261.9373 10 6 228.9296 10 6 175 272.1948 10 6 239.1744 10 6 176 264.6556 10 6 223.0571 10 6 177 264.6437 10 6 223.0505 10 6 178 270.1237 10 6 227.9723 10 6 179 276.0329 10 6 233.2917 10 6 180 282.3657 10 6 239.0265 10 6 181 289.1393 10 6 245.1954 10 6 182 296.4136 10 6 251.8572 10 6 183 304.2321 10 6 259.0647 10 6 184 312.6640 10 6 266.8919 10 6 185 322.3443 10 6 275.9539 10 6 186 332.2633 10 6 285.3273 10 6 187 343.0453 10 6 295.6065 10 6 188 354.7812 10 6 306.9268 10 6 189 367.5947 10 6 319.4411 10 6 190 381.5798 10 6 333.2656 10 6 191 396.7887 10 6 348.4879 10 6 192 368.8485 10 6 311.5355 10 6 193 368.8362 10 6 311.5120 10 6 194 376.1735 10 6 318.1291 10 6 195 384.0696 10 6 325.2934 10 6 196 392.4961 10 6 332.9710 10 6 197 401.5216 10 6 341.1971 10 6 198 411.1681 10 6 350.0283 10 6 199 421.4977 10 6 359.6016 10 6 200 432.5966 10 6 369.9675 10 6 201 445.4332 10 6 381.9518 10 6
data sheet adn2817/adn2818 rev. e | page 37 of 40 code low limit high limit 202 458.5027 10 6 394.3307 10 6 203 472.7012 10 6 407.9363 10 6 204 488.2673 10 6 422.8489 10 6 205 505.2599 10 6 439.4259 10 6 206 523.874 5 10 6 457.8593 10 6 207 544.3897 10 6 478.3487 10 6 208 529.3112 10 6 446.1142 10 6 209 529.2874 10 6 446.1009 10 6 210 540.2475 10 6 455.9446 10 6 211 552.0658 10 6 466.5834 10 6 212 564.7314 10 6 478.0529 10 6 213 578.2786 10 6 490.3908 10 6 214 592.8272 10 6 503.7145 10 6 215 608.4642 10 6 518.1295 10 6 216 625.3279 10 6 533.7838 10 6 217 644.6885 10 6 551.9079 10 6 218 664.5266 10 6 570.6547 10 6 219 686.0907 10 6 591.2129 10 6 220 709.5624 10 6 613.8536 10 6 221 735.1895 10 6 638.8822 10 6 222 763.1596 10 6 666.5311 10 6 223 793.5774 10 6 696.9759 10 6 224 737.6969 10 6 623.0711 10 6 225 737.6724 10 6 623.0240 10 6 226 752.3471 10 6 636.2582 10 6 227 768.1392 10 6 650.5869 10 6 228 784.9921 10 6 665.9419 10 6 229 803.0432 10 6 682.3941 10 6 230 822.3363 10 6 700.0567 10 6 231 842.9953 10 6 719.2032 10 6 232 865.1931 10 6 739.9350 10 6 233 890.8664 10 6 763.9035 10 6 234 917.0055 10 6 788.6615 10 6 235 945.4024 10 6 815.8726 10 6 236 976.5346 10 6 845.6979 10 6 237 1.0105 10 9 878.8518 10 6 238 1.0477 10 9 915.7186 10 6 239 1.0888 10 9 956.6975 10 6 240 1.0586 10 9 892.2284 10 6 241 1.0586 10 9 892.2018 10 6 242 1.0805 10 9 911.8893 10 6 243 1.1041 10 9 933.1668 10 6 244 1.1295 10 9 956.1059 10 6 245 1.1566 10 9 980.7817 10 6 246 1.1857 10 9 1.0074 10 9 code low limit high limit 247 1.2169 10 9 1.0363 10 9 248 1.2507 10 9 1.0676 10 9 249 1.2894 10 9 1.1038 10 9 250 1.3291 10 9 1.1413 10 9 251 1.3722 10 9 1.1824 10 9 252 1.4191 10 9 1.2277 10 9 253 1.4704 10 9 1.2778 10 9 254 1.5263 10 9 1.3331 10 9 255 1.5872 10 9 1.3940 10 9 256 1.4754 10 9 1.2461 10 9 257 1.4753 10 9 1.2460 10 9 258 1.5047 10 9 1.2725 10 9 259 1.5363 10 9 1.3012 10 9 260 1.5700 10 9 1.3319 10 9 261 1.6061 10 9 1.3648 10 9 262 1.6447 10 9v 1.4001 10 9 263 1.6860 10 9 1.4384 10 9 264 1.7304 10 9 1.4799 10 9 265 1.7817 10 9 1.5278 10 9 266 1.8340 10 9 1.5773 10 9 267 1.8908 10 9 1.6317 10 9 268 1.9531 10 9 1.6914 10 9 269 2.0210 10 9 1.7577 10 9 270 2.0955 10 9 1.8314 10 9 271 2.1776 10 9 1.9134 10 9 272 2.1172 10 9 1.7845 10 9 273 2.1171 10 9 1.7844 10 9 274 2.1610 10 9 1.8238 10 9 275 2.2083 10 9 1.8663 10 9 276 2.2589 10 9 1.9122 10 9 277 2.3131 10 9 1.9616 10 9 278 2.3713 10 9 2.0149 10 9 279 2.4339 10 9 2.0725 10 9 280 2.5013 10 9 2.1351 10 9 281 2.5788 10 9 2.2076 10 9 282 2.6581 10 9 2.2826 10 9 283 2.7444 10 9 2.3649 10 9 284 2.8382 10 9 2.4554 10 9 285 2.9408 10 9 2.5555 10 9 286 3.0526 10 9 2.6661 10 9 287 3.1743 10 9 2.7879 10 9
adn2817/adn2818 data sheet rev. e | page 38 of 40 outline dimensions 3.65 3.50 sq 3.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant t o jedec s t andards mo-220-vhhd-2 32 9 8 1 25 24 17 16 coplanarit y 0.08 3.50 ref 0.50 bsc pin 1 indic a t or pin 1 indic a t or 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 ty p 1.00 0.85 0.80 0.05 max 0.02 nom sea ting plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq 0.60 max 0.60 max 0.25 min 04-13-2012- a t op view exposed p ad bot t om view figure 43 . 32 - lead lead frame chip scale package [lfcsp _vq ] 5 mm 5 mm body, very thin quad (cp - 32 - 4 ) dimensions shown in millimeters ordering guide mode l 1 temperature range package description package option ordering quantity adn2817acpz ? 40c to +85c 32 - lead lfcsp _vq cp - 32 - 4 490 adn2817acpz - rl ? 40c to +85c 32- lead lfcsp_vq , 13 tape an d reel cp -32-4 5,000 adn2817acpz - rl7 ? 40c to +85c 32- lead lfcsp_vq , 7 tape and reel cp -32-4 1,500 adn2818acpz ? 40c to +85c 32 - lead lfcsp_vq cp - 32 - 4 490 adn2818acpz - rl ? 40c to +85c 32- lead lfcsp_vq , 13 tape and reel cp -32-4 5,000 adn2818acpz - rl7 ? 40c to +85c 32- lead lfcsp_vq , 7 tape and reel cp -32-4 1,500 eval - adn2817ebz evaluation board for adn2817 eval - adn2818ebz evaluation board for adn2818 1 z = rohs compliant part.
data sheet adn2817/adn2818 rev. e | page 39 of 40 notes
adn2817/adn2818 data sheet rev. e | page 40 of 40 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as define d by philips. ? 2007 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06001 - 0- 1/13(e)

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